Conventionally, a system LSI in which a plurality of bus masters and a shared memory are connected by a plurality of system buses has been implemented (e.g., patent reference 1). A processor, DSP (Digital Signal Processor), DMAC (Direct Memory Access Controller), and the like are known as the bus masters. In a system LSI of this kind, a memory controller for controlling access from a plurality of system buses to a shared memory is an essential device.
This memory controller is required to achieve high system performance while maintaining high versatility to various systems different in system bus configuration, memory configuration, and the like. For this purpose, it is important for the memory controller to control access while ensuring the band width and real-time processing of the shared memory.
The conventional memory controller can be connected to only a specific system bus formed in common to various systems, or the priority of connection of each system bus is fixed.    Patent reference 1: Japanese Patent Laid-Open No. 11-120154